Dynamic PLA read-only memories include a matrix of PLA lines and address/data lines. For example, the PLA lines may be laid out in rows with the address and data lines forming columns of the matrix. The PLA operates by precharging the PLA lines and the data lines in a precharge operation, which is then followed by an evaluate operation in which the PLA lines enabled by the present address provide a logic 1 level, in the data section of the memory, which operates to discharge the data lines coupled to the enabled PLA lines by n-channel pull down transistors. Thus, the selected data lines, which were precharged to a logic 1 level, are pulled to ground potential by the selected PLA lines. After the data lines have stabilized, the logic level on the data lines is captured in a latch.
A critical timing operation is the latching of the state of the data lines. The state of the data lines does not change immediately when the evaluation operation begins due to the capacitance on the PLA lines and the data lines. Also, due to leakage, the non-selected data lines will eventually lose their charge and become a logic 0 level even though not selected in the current read operation. Therefore, the logic state of the data lines must be captured in a latch within an appropriate time window after the evaluate operation begins.
This delay time, between the start of the evaluation cycle and the time window when the correct data is on the data lines, is a function of the manufacturing process and may vary from manufacturing lot to manufacturing lot. Also, in certain systems, an appropriate external clock pulse, which is normally used to provide this timed delay, is not readily available.
Therefore, it can be appreciated that a dynamic PLA timing circuit which compensates for manufacturing process variations and which does not require an external clock is highly desirable.